Digital System Design With Vhdl

Introduction to the design of complex digital systems using hardware description languages. Emphasizes the design methodology based on the partitioning of a digital system into a datapath and control unit. Introduces a clear sequence of steps leading from specification to synthesizable, register transfer level (RTL), and fully verified HDL code. Covers VHDL for digital circuit design, including dataflow, structural, and behavioral coding styles. Introduces and illustrates the concepts of VHDL simulation, verification, synthesis, mapping, placing, routing, timing analysis and performance optimization. Requires semester long project devoted to the design of a complex digital system using VHDL as a hardware description language and FPGA as an implementation platform. Offered by Electrical & Comp. Engineering. May not be repeated for credit.